1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a method of fabricating a semiconductor device having a trench isolation oxide film.
2. Related Background Art
A semiconductor device of an SOI (Silicon On Insulator) structure (hereinbelow, called an SOI device) formed on an SOI substrate in which a buried oxide film and an SOI layer are formed on a silicon substrate has characteristics such as reduced parasite capacity, high-speed operation, and low power consumption and is used for a portable device and the like.
Also for a bulk device directly formed on a silicon substrate, microfabrication technology and high integration technique progress conspicuously, and the speed of development of the bulk device is increasing.
In association with a progress of a device technique, the concentration of a channel impurity and that of a source/drain impurity are getting higher and, moreover, a sharp impurity profile is requested more and more. Consequently, there is a tendency that heat treatment after implanting impurities is performed at low temperature in short time.
On the other hand, for a device having a trench isolation structure formed by filling a trench in a silicon layer with an insulating material, heat treatment at high temperature for long time is indispensable to form the isolation structure.
As an example of the SOI device, FIG. 92 shows a partial sectional configuration of an SOI device 70 in which MOS transistors are electrically isolated from each other by a trench.
In FIG. 92, in an SOI substrate in which a buried oxide film 102 and an SOI layer 103 are formed on a silicon substrate 101, an N-channel type MOS transistor (NMOS transistor) NM1 and a P-channel type MOS transistor (PMOS transistor) PM1 are formed on SOI layer 103 and are electrically completely isolated from each other by an isolation oxide film 104. Isolation oxide film 104 is provided so as to surround NMOS transistor NM1 and PMOS transistor PM1.
Each of NMOS transistor NM1 and PMOS transistor PM1 is constructed by a source/drain region SD formed in SOI layer 103, a channel forming region CH, a gate oxide film GO formed on channel forming region CH, a gate electrode GT formed on gate oxide film GO, and a side wall oxide film SW covering side faces of gate electrode GO.
In SOI device 70, NMOS transistor NM1 and PMOS transistor PM1 are not only independent of each other by isolation oxide film 104 in SOI layer 103 but also completely isolated from other semiconductor devices and the like. The SOI device 70 has, therefore, a structure in which latch-up does not occur in the transistors in theory.
In the case of fabricating an SOI device having a CMOS transistor, there is consequently an advantage that the minimum isolation width determined by the microfabrication technology can be used and the chip area can be reduced. However, there are various problems caused by a substrate floating effect, such as accumulation of carriers (holes in the NMOS) generated by an impact ionization in the channel forming region, occurrence of a kink due to the accumulated carriers, deterioration in operation breakdown voltage resistance, and occurrence of frequency dependency of delay time caused by an unstable potential of the channel forming region.
Consequently, a partial trench isolation structure has been devised. FIG. 93 shows a partial sectional configuration of an SOI device 80 having a partial trench isolation structure (PTI structure).
In FIG. 93, NMOS transistor NM1 and PMOS transistor PM1 are provided on S0I layer 103 and are isolated from each other by a partial isolation oxide film 105 under which a well region WR is formed. Partial isolation oxide film 105 is disposed so as to surround NMOS transistor NM1 and PMOS transistor PM1.
A structure for electrically completely isolating devices by a trench oxide film reaching buried oxide film 102 like isolation oxide film 104 in SOI device 80 will be called a full trench isolation structure (FTI structure) and the oxide film will be called a fall isolation oxide film.
Although NMOS transistor NM1 and PMOS transistor PM1 are isolated from each other by partial isolation oxide film 105, carries can move via well region WR under partial isolation oxide film 105. The carriers can be prevented from being accumulated in a channel forming region, and the potential of the channel forming region can be fixed via well region WR. Consequently, there is an advantage such that the various problems due to the substrate floating effect do not occur.
As an SOI device having a PTI structure with further improved reliability of a MOS transistor, a MOS transistor 90 to be described hereinbelow can be mentioned.
A method of fabricating MOS transistor 90 will be described hereinbelow with reference to FIGS. 94 to 101. The configuration of MOS transistor 90 is shown in FIG. 101 for explaining the final process.
First, as shown in FIG. 94, by an SIMOX method for forming buried oxide film 102 by oxygen ion implantation, bonding, or the like, the SOI substrate constructed by silicon substrate 101, buried oxide film 102, and SOI layer 103 is prepared.
An oxide film 106 having a thickness of 10 to 30 nm (100 to 300 Å) is formed by CVD or thermal oxidation and, after that, a nitride film 107 having a thickness of 30 to 200 nm (300 to 2000 Å) is formed. Subsequently, a resist mask RM1 is formed on nitride film 107 by patterning. Resist mask RM1 has an opening for forming a trench.
Subsequently, by using resist mask RM1 as a mask, nitride film 107, oxide film 106, and SOI layer 103 are patterned by etching, thereby forming a partial trench TR in SOI layer 103 as shown in FIG. 95. The etching is performed not to completely etch SOI layer 103 to expose the buried oxide film 102 but the etching parameters of the etching are adjusted so that SOI layer 103 having a predetermined thickness remains on the bottom of the trench.
Since partial trench TR is formed so as to extend almost perpendicular to silicon substrate 101 with a predetermined width, device isolation which maintains fineness can be performed without deteriorating integration.
In the process shown in FIG. 96, an oxide film having a thickness of about 500 nm (5000 Å) is deposited, nitride film 107 is polished part way by CMP (Chemical Mechanical Polishing) and, after that, nitride film 107 and oxide film 106 are removed, thereby forming partial isolation oxide film 105. The region on the left side of the partial isolation oxide film 105 is set as a first region R1 in which a transistor having a low threshold voltage, and the region on the right side of the partial isolation oxide film 105 is set as a second region R2 in which a transistor having a general threshold voltage and high reliability is formed.
Subsequently, oxide film OX101 is formed on the entire face of SOI layer 103 in the process shown in FIG. 97. The thickness of oxide film OX101 is 1 to 4 nm (10 to 40 Å). After that, a resist mask RM2 is formed so as to cover second region R2, and a semiconductor impurity is ion implanted into SOI layer 103 in first region R1 via oxide film OX101. The implantation parameters in this case are parameters for forming a transistor having a low threshold voltage. In the case of forming, for example, an NMOS transistor, ions of boron (B) are implanted with an energy of 5 to 40 keV and a dose of 1×1011 to 3×1011/cm2. Prior to the process, a process of forming a well region by implanting boron ions with an energy of 30 to 100 keV and a dose of 1×1012 to 1×1014/cm2 is performed.
In the process shown in FIG. 98, a resist mask RM3 is formed so as to cover first region R1, and a semiconductor impurity is introduced into SOI layer 103 in second region R2 via oxide film OX101 by ion implantation. The implantation parameters in this case are parameters for forming a transistor having a general threshold voltage. In the case of forming, for example, an NMOS transistor, ions of boron (B) are implanted with an energy of 5 to 40 keV and a dose of 3×1011 to 5×1011/cm2.
In the process shown in FIG. 99, a resist mask RM4 is formed so as to cover second region R2, and oxide film OX101 in first region R1 is removed.
After removing resist mask RM4, an oxide film is formed in the whole area in the process shown in FIG. 100. At this time, an oxide film OX102 having a thickness of 2 to 4 nm (20 to 40 Å) is formed in region R1, and an oxide film OX103 is obtained by increasing the thickness of oxide film OX101 in region R2. After that, in the whole area, a polycrystalline silicon layer (hereinbelow, called a polysilicon layer) PS1 serving as a gate electrode is formed.
Subsequently, in the process shown in FIG. 101, by patterning polysilicon layer PS1 and oxide films OX102 and OX103, gate electrodes GT1 and GT2 and gate oxide films GO1 and GO2 are formed and, by forming a side wall oxide film SW and source/drain layer SD, NMOS transistors NM3 and NM4 are formed. Under partial isolation oxide film 105, well region WR exists.
On NMOS transistors NM3 and NM4, an interlayer insulating film is formed. A plurality of contact holes (not shown) penetrating the interlayer insulating film and reaching source/drain layer SD are formed. In such a manner SOI device 90 is configured.
As described above, the SOI device having the PTI structure is being widely used as a device capable of solving various problems caused by the substrate floating effect. However, there is a case that, in the well region under the partial isolation oxide film, the impurity concentration decreases due to a segration phenomenon at the time of forming an oxide film, and the conduction type reverses. In order to stop this, channel stop implantation for implanting impurities of the same conduction type as that of the impurities to the well region is performed. However, as described above, at the time of forming the trench isolation structure, heat treatment of long time at high temperature is indispensable. Consequently, even if the channel stop implantation is performed before the trench isolation structure is formed, there is the possibility that the impurities are diffused in the heat treatment performed after that, the profile is disturbed, and an intended effect cannot be obtained.
As a method of solving the problem, a method of implanting impurities after forming the trench isolation structure can be mentioned. However, in this case, a problem arises such that it is difficult to implant impurities of high concentration into only the region under the trench isolation oxide film.
Specifically, as shown in FIG. 102, in the case of forming partial isolation oxide film 105 on the surface of SOI layer 103 and implanting ions through partial isolation oxide film 105 into the region under the partial isolation oxide film 105, the impurities of high concentration are also introduced into an active region AR in which a semiconductor device such as a MOS transistor is to be formed and an impurity layer XL is formed.
This happens for the reason that an isolation step (for example, 20 nm) is low, which is specified by the height L of a portion projected from the main surface of SOI layer 103, of partial isolation oxide film 105. If implantation is performed with an energy that impurities are implanted through partial isolation oxide film 105 and the peak of an impurity profile is formed in the well region under partial isolation oxide film 105, impurity layer XL of high concentration is formed also in active region AR. The conduction type of impurity layer XL is opposite to that of the source/drain layer.
As a result, it becomes difficult to adjust the threshold value of a MOS transistor and to make the source/drain layer of the MOS transistor or a depletion layer formed around a PN junction of the source/drain layer reach buried oxide film 102.
FIG. 103 shows a configuration in which a MOS transistor is formed in active region AR. Due to existence of impurity layer XL, impurities of the source and drain are canceled off, and source/drain region SD does not reach buried oxide film 102. The depletion layer formed around the PN junction of the source/drain layer cannot also reach buried oxide film 102 due to the existence of impurity layer XL.
On the other hand, when the isolation step of partial isolation oxide film 105 is made large, impurity layer XL of high concentration can be prevented from being formed in active region AR. From the viewpoint of microfabrication of a semiconductor device, it is desirable that the isolation step is set to 20 nm or less.